constrained-random

OSVVM Utility Library: AlertLogPkg, CoveragePkg, RandomPkg, ScoreboardGenericPkg, MemoryPkg, TbUtilPkg, TranscriptPkg, ...

Python packages providing a library for Verification Stimulus and Coverage

Constrained random stimuli generation for C++ and SystemC

A Python package for creating and solving constrained randomization problems.

A reusable UVM testbench for AMBA IP, with constrained transaction generation, a protocol driver and monitor, a reference scoreboard, assertions and functional coverage, written in SystemVerilog.

Coverage-driven verification of an asynchronous FIFO across independent write and read clocks, using constrained-random stimulus, a reference scoreboard, CDC checks, assertions and cross coverage in SystemVerilog.

RV32IM RISC-V CPU core with a full UVM verification environment and ISA-compliance via Spike (DPI-C): constrained-random, SVA, coverage, Python debug tools, and CI.

SystemVerilog and UVM verification of an 8x8 SRAM memory controller with coverage, scoreboard, regression scripts, and bug-demo dashboard.

UVM-based verification environment for a 5-stage RV32I RISC-V pipeline using constrained-random testing, DPI-C golden reference modeling, assertions, scoreboarding, functional coverage, and 20-seed QuestaSim regression debugging.

UVM testbench for verifying a packet router using the YAPP (Yet Another Packet Protocol)

SRAM subsystem verification using SystemVerilog UVM, SVA assertions, scoreboard, functional coverage, and 20-seed QuestaSim regression evidence from EDA Playground.

AXI4 Memory Controller UVM Verification Environment with real Siemens Questa seed-1 simulation logs, scoreboard checks, functional coverage summaries, and documented burst-read debug fix.

Dual-clock asynchronous FIFO in SystemVerilog with layered verification: constrained-random testbench, functional coverage, SVA, SymbiYosys formal spec

Explorations in Uniform Sampling of SMT2 Constraints

Multi-state Mealy/Moore FSM in SystemVerilog with SVA assertions, constrained-random testbenches, and functional coverage — synthesizable on Xilinx FPGAs

Learning project: parameterized FIFO RTL with an evolving SystemVerilog/UVM verification environment.

Public portfolio of APB4 and AXI4 verification methodology using SystemVerilog, UVM, SVA and coverage.

SystemVerilog memory verification using constrained-random stimulus, mailboxes, monitors, and a reference checker.

Backpressure-safe 1-stage valid-ready pipeline in SystemVerilog with constrained-random verification, assertions (SVA), and waveform validation.

Synchronous FIFO RTL with a full UVM testbench: constrained-random stimulus, golden-model scoreboard, functional coverage and SVA assertions. 100% functional coverage.