apb

Code generation tool for control and status registers

Control and status register code generator toolchain

Ansible Service Broker

Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

THIS REPO IS MIGRATING: https://github.com/automationbroker/apb

The AHB to APB bridge is an AHB slave and the only APB master which provides an interface between the highspeed AHB and the low-power APB. Read and write transfers on the AHB are converted into equivalent transfers on the APB.

Parameterised Asynchronous AHB3-Lite to APB4 Bridge.

Verification IP for AMBA APB Protocol

This repo contains a collection of Verilog+System Verilog+RTL+UVM+Protocols Projects

APB master and slave developed in RTL.

Claude Code / Codex CLI skill that scaffolds a runnable UVM testbench (APB / AHB-Lite / AXI4-Lite + generic-bus fallback) from an IP spec and register table, with a UVM-sequence flow for DV and a tb_api:: task BFM for DE.

To design test bench of the APB protocol

Flaws' APB Reloaded Config

OVIP -- open VIPs. Apache-2.0 UVM verification IPs for interconnect protocols. AXI3/AXI4/AXI4-Lite, AXI-Stream, and APB3/APB4 today; AHB/OCP planned.

General Purpose IO with APB4 interface

Common SystemVerilog RTL modules for RgGen

UVM-based functional verification of an APB-based UART Master Core RTL. Includes multi-agent environment, assertions, coverage collection, and multiple test scenarios (full/half duplex, parity, framing, timeout errors) achieving 100% functional coverage and protocol compliance.

APB4 Multiplexor

APB verification using UVM

A reusable UVM testbench for AMBA IP, with constrained transaction generation, a protocol driver and monitor, a reference scoreboard, assertions and functional coverage, written in SystemVerilog.